Sh dev

=Writing code for the SuperH microcontrollers != Here's a collection of notes that should help write kernels and modify stock firmware. The idea is to supplement or reword the less obvious parts of the Datasheets.

Advanced Timer Unit-II (ATU-II)
"Advanced Timer" indeed. Very complex unit with over 10 independant timers, each with a different set of features.

Interrupts
Channel 1 seems to offer interrupts for "compare-on-match", i.e. fire an interrupt when the free-running counter compares equal to one of the GRx registers (like (TCNT1A == GRA) for example). I think this only works when the associated bits of the TIOR registers are configured to enable pin outputs. In other words, To have some kind of interval interrupt, the best solution I've found is
 * TIOR1A = 0 "compare-match disabled; pin output undefined"
 * TSR1A.IMF* bits do not cause an interrupt
 * use TCNT1B as a freerunning counter
 * set OCR as the interval
 * set TIER1B.CME to enable compare-match interrupt